Cadence and Nvidia unveil platform with 40x faster RTL validation

Signals Inbox·July 28, 2026·AI DevTools

Cadence and Nvidia say their autonomous engineering platform can shrink a typical five-week RTL validation cycle to less than one day. The real shift is not simply that AI can write chip code. It is that agents are starting to run the slow testing, debugging, and simulation loops that decide how quickly a chip can reach production.

Q1What did Cadence officially announce?

In its official announcement, Cadence introduced a Level-5 autonomous virtual engineer for chip design. It combines Cadence ChipStack AI Super Agents and design tools with Nvidia Nemotron models and the Nvidia OpenShell runtime. The agent can launch simulations, study failures, change its approach, and keep working with limited human direction.

Q2Where does the 40x number come from?

Cadence says its agents can coordinate hundreds of runs using Xcelium Logic Simulation and Jasper Formal Verification. In its example, that reduces a typical RTL validation loop from around five weeks to less than one day. That is the 40x claim. Instead of an engineer repeatedly starting tests and sorting through failures, the agent keeps the loop running by itself.

Q3What is RTL validation?

RTL is the code-like description of how a chip should behave. Before anyone manufactures the chip, engineers run huge numbers of tests to find logic errors and unexpected behavior. This can take weeks because every failure must be understood, fixed, and tested again. A missed bug can lead to an expensive chip redesign, so teams cannot simply skip the work.

Q4Is the AI designing the whole chip alone?

Not exactly. Engineers still define the goals, review important decisions, and decide what is safe to ship. The change is that the AI can now handle a longer chain of work. It can create tests, launch tools, inspect results, debug problems, and repeat the process. That is much closer to an autonomous junior engineering team than a simple coding assistant.

Q5Why does Nvidia matter here?

Nvidia provides the Nemotron models and the runtime that lets agents use engineering tools inside controlled environments. Its related ACE-RTL system reached a 97.1% average pass rate across nine RTL task categories and used up to 71% fewer tokens per iteration than comparison methods. Cadence brings the commercial tools and chip-design workflows where those agents can do useful work.

Q6Why is this happening now?

Chip design is getting more complicated while expert engineering time remains limited. Nvidia says its own engineers already use billions of compute hours each year to run millions of design tests. Cadence first pushed ChipStack toward Level-5 autonomy in June, then launched an agent for circuit boards and advanced packaging in July. The pieces are now being joined into one silicon-to-system platform.

Q7So what really changes?

The expensive part of chip development may shift from waiting on people to buying enough compute for agents to test more ideas. Teams could explore more designs, catch errors sooner, and shorten the path to production. The bigger signal is that AI agents are leaving chat windows and entering high-value engineering loops where one saved week can be worth a lot of money.